Industrial Internet of Things (IIoT) offers smart infrastructure and hyper-connected devices with sensing, processing and networking capabilities. These systems will generate incredible amounts of Data, sharing the same network. Thus, it is necessary to ensure that the real-time and critical-mission messages are transferred within strict bounds of latency and reliability regardless of other network traffic.
Deterministic Ethernet solutions, like TSN, deliver streams with guaranteed bandwidth and deterministic latency. There are many features involved in the multiple standards currently under development.
Time Sensitive Networking (TSN) is the name of the IEEE 802.1 Task Group responsible for standards at Data Link Layer. This group provides the specifications that will allow time-synchronized and low latency streaming services through IEEE 802 networks.
TSN is evolving and it is targeting different sectors, like Automotive, Industry, Broadcasting and Aerospace. Therefore, it is expected switching implementations that combine a subset of the available standards and features. This flexibility can be achieved through reconfigurable logic (FPGAs), HDL IPs and embedded software.
Multiport Time Sensitive Networking (MTSN) Switch IP core supports IEEE 802.1AS to provide precise time synchronization of the network nodes to a reference time by synchronizing distributed local clocks with a reference and IEEE 802.1Qbv for a enhanced traffic scheduling.
- Full-duplex 10/100/1000 Mbps Ethernet Interfaces
- Configurable 3 to 16 Ethernet ports
- MII/RMII/GMII/RGMII/SGMII/QSGMII Physical Layer device (PHY) interfaces
- Different data rate supported for each port
- Dynamic MAC Table with automatic MAC addresses learning and aging (up to 2048 entries)
- Static MAC Table (up to 2048 entries)
- Jumbo Frame Management
- Broadcast/Multicast Storm Protection
- Per-Port Rate limiting (Broadcast, Multicast and Unicast traffic)
- Port-based VLAN support
Time Sensitive Networking
- IEEE 802.1AS for Time Synchronization Layer
- IEEE 802.1Qbv for Scheduled Traffic
- Time Aware Shaper: Configurable number of time slots
- Credit Based Shaper: Configurable bandwidth reservation for each traffic class
- IEEE 802.1Qcc for Network Management
- RESTCONF (RESTful API) for managing YANG data
- MDIO, UART, AXI4-Lite or CoE (Configuration-over-ethernet) management interfaces
- Configuration-over-Ethernet (COE): Full access to internal registers through the same Ethernet link that connects to the CPU
- Drivers are provided with IP Core purchase
- 7-Series (Zynq, Spartan, Artix, Kintex, Virtex)
- Ultrascale (Kintex, Virtex)
- Ultrascale+ (Zynq MPSoC, Kintex, Virtex)
Embedded Development Suite
A hardware development platform is available. Latest documentation, design support ﬁles, reference design source ﬁles and tools are available for download free of charge.
* Device supported by the free Xilinx Vivado WebPACK tool.
Pricing, Availability and Ordering
- Concurrent EDA is the US Distributor for SoC-e.
- Currently Available to US customers only.