IRIG-B Slave Core

IRIGtimeS Block Diagram


IRIGtimeS implements an IRIG 200-04 compliant time synchronization slave on FPGA devices. This IRIG-B slave IP has been designed to support all the IRIG-B coded expressions as well as DCLS and AM modulations in order to provide maximum flexibility.

This IRIG-B slave IP receives IRIG-B frames each second, getting the time information (seconds, minutes, hours, days, years, control functions and binary straight seconds) depending on the IRIG-B time code. This IP implements a 64-bit internal timer in order to provide the timestamp (in seconds) and nanoseconds value. This timer is synchronized in value and frequency with the received IRIG-B time information. This IP has been designed to provide autonomous operation, requiring as less configuration as possible.

Key Features

  • IRIG 200-04 compliant time synchronization slave
  • Support for DCLS and AM modulations
  • Support for all IRIG-B coded expressions, including year information, control functions and straight binary seconds
  • Sub-microsecond synchronization with teh IRIG-B master
  • 640bit internal timer synchronized in time and frequency with the IRIG-B master
  • 32-bit for timestamp in seconds and 32-bit for nanoseconds
  • Periodic pulse output for testing
IRIGtimeS I/O Diagram

Supported FPGAs

  • 6-Series (Spartan, Virtex)
  • 7-Series (Zynq, Spartan, Artix, Kintex, Virtex)
  • Ultrascale (Kintex, Virtex)
  • Ultrascale+ (Zynq MPSoC, Kintex, Virtex)

Embedded Development Suite

A hardware development platform is available. Latest documentation, design support files, reference design source files and tools are available for download free of charge.

* Device supported by the free Xilinx Vivado WebPACK tool.

Pricing, Availability and Ordering

  • Concurrent EDA is the US Distributor for SoC-e.
  • Currently Available to US customers only.
  • Please email Ray at This e-mail address is being protected from spambots. You need JavaScript enabled to view it with questions / quotes / orders.


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