FPGAs, Edge AI, and High-Speed Imaging Demos: What's Running in the Concurrent EDA Lab

A lot of FPGA work is invisible by design. The logic sits inside a camera, a frame grabber or a defense system, and the customer only sees that the thing works and keeps up. That’s good for the customer and bad for anyone trying to explain what Concurrent EDA does. Here is a look at some demonstrations that highlight just that.

A UDP Router That Lives Entirely in the Fabric

The first demo shows two FPGAs, a Zynq and an Artix UltraScale+, passing 12 separate channels of data to each other over Ethernet. Everything happens in the FPGA fabric. There’s no CPU in the path and no Linux drivers to write.

The key piece here is Concurrent EDA’s UDP router. It packetizes each channel and sends it out a single link on its own UDP port, and the receiving FPGA pulls each stream back into the right channel. The FPGA designer never has to deal with packets. Because it’s standard UDP, the other end doesn’t have to be an FPGA.

“I could send this to 12 different Python programs on a PC, and it would all work,” says Hoare.

That lets one link carry very different traffic, from control, UART and debug channels to a high-speed ADC or camera stream. A temperature reading sent every 100 milliseconds rides alongside it all without getting dropped. The router is deterministic and runs at full line rate as long as the 10 Gb link isn’t oversubscribed. The demo shows close to 8 Gb/s. It also lets FPGAs without a built-in processor talk to the network directly.

Hoare’s take on doing the same thing in software: “The performance would just be miserable.”

The router is available as an IP core and is also used in Concurrent EDA’s custom designs.

High-Speed Capture of a Spinning LED Display

Next is a spinning LED blade display showing an image of a baseball. To the eye, it reads as a steady picture. Captured at high speed and slowed down, it breaks apart into individual LEDs changing value as the blade sweeps around.

It’s a simple way to see what a high frame rate gets you: detail that happens far too fast for a person to follow.

Laser Tracking at 2,200 Frames per Second

This one runs inside the camera. The FPGA tracks a moving laser dot at 2,200 frames per second and draws a bounding box around it in real time. There’s no host PC in the loop doing the tracking.

RFSoC: Generate, Capture, Separate

The RFSoC segment moves from imaging into radio frequency. Two sine waves are combined and sent out. The RFSoC captures the combined signal at gigasample-per-second rates, runs an FFT to find which frequencies are present, and channelizes them to pull each one back out. If you work in RF, check this part out.

An Image Signal Processor Running at 2,000+ fps

Here the full image signal processing pipeline runs on a PCIe card at more than 2,000 frames per second. That covers everything from debayering through white balance and color correction, with a live color histogram on screen.

The next step is adding a GigE Vision 3.0 front end to that card. A 100G camera sending RDMA data would feed the card directly. All the processing happens as the data arrives, so by the time frames land in host memory they’re already processed. The CPU and GPU don’t give up any cycles for it. Hoare describes it as “not a frame grabber, per se, it’s a frame processor.”

AI Engine Tiles Doing Pose Detection

In this demo, a MIPI camera feeds straight into the FPGA. The FPGA runs the ISP so the color looks right, then hands frames to the AI engine tiles for feature and pose detection. The ARM cores on the same chip draw the overlay, and the result goes out over HDMI. Programmable logic, AI tiles and software each do the job they’re best at, all on one device. A second, lower-resolution version runs a different model. It skips eye detection but still tracks pose well.

ALECS: Pose, Eyes and Barcodes

The last segment uses three USB cameras and Allied Vision’s Alecs open smart camera. It runs the same pose detection, adds eye detection, and reads barcodes in the same pass.

Bring Us Your Data Challenges

Each of these demos deserves its own deep-dive video, but in the meantime, if one of these looks like the problem sitting on your desk, whether that’s moving a lot of data off an FPGA, processing a 100G camera stream, or putting AI inside a camera, Concurrent EDA would like to hear about it.

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