|Gain full access to the FPGA.
Unlock the full potential of your cameras.
3D Laser Measuring
|The Concurrent HDK will let you embed your own IP into an inexpensive, off-the-shelf Mikrotron® camera under our GigaSens™ brand to achieve accelerated performance at a fraction of the cost of a traditional customized solution. Designed for highresolution, real time imaging applications, these cameras are FPGA programmable-ready with up to 100x the processing power of a high-end PC.
|The Concurrent HDK is a library of critical tools that bring edge functionality to a camera including control, processing, diagnostics, resource analysis and more. By reducing the data sent to the CPU and therefore supplying additional bandwidth, the programmed FPGA eliminates processing bottlenecks and unlocks the full potential of today’s most advanced sensors. This approach is highly suitable for embedded vision in low SWAP applications where it can be used for real-time image processing and camera control.
|Leveraging the Concurrent HDK along with Xilinx’s Vivado Design Suite allows you to easily develop custom image processing algorithms for implementation in FPGAs that scale to the future needs of machine vision applications. The development environment is remarkably straightforward and simple. No extensive experience with gate architecture or bit level manipulation is required. And all software is included with your camera package.
CXP AND 10GigE
Concurrent optimizes FPGAs for Mikrotron CoaXPress 2.0 and 10 GigE high-speed machine vision cameras. For more than 40 years Mikrotron cameras have met the industry’s most demanding quality and reliability standards. Mikrotron quality management procedures have been certified ISO 9001:2015.
|The solution to processing high-resolution images is to use a large FPGA that is user-programmable. Don’t procrastinate the computations, do them in real-time as data comes off the sensor. This results in increased performance and a low system cost.
|Sensor: LUX19HS sensor capable of 2K FPS with 10-bit pixel resolution.
User-Logic: Most FPGA is unused and available for custom processing. Input and outputs are standard AXI Streams for ease of development. The stream also has a Start of Frame indicator within the AXI Stream interface.
Network Interface: The network interface is either 4x CXP12 or 10GigE Vision.
|Control: Controlling the Sensor is through the standard CXP2 / GigE Vision interface. Along with standard ensor controls, 32 additional registers are accessible to User-Logic. These registers allow parameters to be passed in from host software to the User-Logic.
Memory: For advanced processing, there is 2GB of DRAM available to user-logic through a standard AXI port.
|Simulation: Part of the HDK is a simulation environment that enables users to simulate their logic using test images. It simulates within the free Vivado WebPack software simulator using a pre-built test-bench that reads in images, processes them, and outputs them.
|Example Design: The HDK includes a User-Logic design example that increases the gain of the image by adding a fixed amount to each pixel.
|Custom Design: Accelerate your time-to-market with a custom design. If you know what you want but would rather leave it to the experts, Concurrent EDA is here to help. Our experts have implemented extremely
|complex, real-time FPGA designs for decades and are ready, willing and able to meet your needs. You provide the test images and specifications, and Concurrent EDA will create a custom camera just for you.
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